Audio amplifiers are used in audio output apparatus for driving speakers, for example, disclosed by U.S. Pat. Nos. 7,714,660 and 7,701,294 and U.S. Pat. Publication No. 2011/0123048. FIG. 1 shows a conventional two channel audio amplifier for driving speakers 16 and 18, which includes amplifying circuits 10 and 13, power stages 12 and 14, a gain setting circuit 20 and a dual mode charge pump 22. The amplifying circuit 10 and power stage 12 establish a right channel audio amplifier for generating an output signal SOR responsive to an input audio signal Sa1 to drive the speaker 16, and the amplifying circuit 13 and the power stage 14 establish a left channel audio amplifier for generating an output signal SOL responsive to an input audio signal Sa3 to drive the speaker 18. Each of the speakers 16 and 18 may be a loudspeaker or an earphone.
An operational amplifier 32 and variable resistors 24, 26, 28 and 30 establish the amplifying circuit 10 for generating differential signals Sa2P and Sa2N responsive to the audio signal Sa1. The variable resistors 24 and 26 are connected to a first input terminal and a second input terminal of the operational amplifier 32, respectively, the variable resistor 28 is connected between the first input terminal and a first output terminal of the operational amplifier 32, and the variable resistor 30 is connected between the second input terminal and a second output terminal of the operational amplifier 32. The power stage 12, which includes an operational amplifier 42 and variable resistors 34, 36, 38 and 40, generates the output signal SOR responsive to the differential signals Sa2P and Sa2N to drive the speaker 16. The variable resistor 34 is connected between the first output terminal of the operational amplifier 32 and a first input terminal of the operational amplifier 42, the variable resistor 36 is connected between the second output terminal of the operational amplifier 32 and a second input terminal of the operational amplifier 42, the variable resistor 38 is connected between the first input terminal and an output terminal of the operational amplifier 42, and the variable resistor 40 is connected between the second input terminal and a ground terminal of the operational amplifier 42.
An operational amplifier 51 and variable resistors 43, 45, 47 and 49 establish the amplifying circuit 13 for generating differential signals Sa4P and Sa4N responsive to the audio signal Sa3. The variable resistors 43 and 45 are connected to a first input terminal and a second input terminal of the operational amplifier 51, respectively, the variable resistor 47 is connected between the first input terminal and a first output terminal of the operational amplifier 51, and the variable resistor 49 is connected between the second input terminal and a second output terminal of the operational amplifier 51. The power stage 14, which includes an operational amplifier 52 and variable resistors 44, 46, 48 and 50, generates the output signal SOL responsive to the differential signals Sa4P and Sa4N to drive the speaker 18. The variable resistor 44 is connected between the first output terminal of the operational amplifier 51 and a first input terminal of the operational amplifier 52, the variable resistor 46 is connected between the second output terminal of the operational amplifier 51 and a second input terminal of the operational amplifier 52, the variable resistor 48 is connected between the first input terminal and an output terminal of the operational amplifier 52, and the variable resistor 50 is connected between the second input terminal and a ground terminal of the operational amplifier 52.
The gain setting circuit 20 provides setting signals G1, G2, G3 and G4 for controlling the variable resistors 24, 26, 28, 30, 34, 36, 38, 40, 43, 44, 45, 46, 47, 48, 49 and 50, to thereby control gains of the amplifying circuit 10 and 13 and the power stages 12 and 14, and thus determines the overall gain of the audio amplifier. In addition, the gain setting circuit 20 determines a gain information Gset according to the overall gain for the dual mode charge pump 22, to control the operation mode of the dual mode charge pump 22. The dual mode charge pump 22 converts an input voltage Vin into a positive voltage Vp and a negative voltage Vn for the audio amplifier. When the dual mode charge pump 22 is in its first mode, Vp=+Vin and Vn=−Vin, and when the dual mode charge pump 22 is in its second mode, Vp=+Vin/2 and Vn=−Vin/2.
Power efficiency is an important parameter that dominates the power consumption of an audio amplifier, especially for a battery powered system. This power efficiency refers to the ratio between the power supplied to the speakers 16 and 18 and the power supplied by the dual mode charge pump 22. As shown in FIG. 1, in the condition that the operation mode of the dual mode charge pump 22 remains unchanged, if the amplitudes of the output signals SOR and SOL reduce, the power efficiency deteriorates. FIG. 2 shows waveforms of the positive voltage Vp, the negative voltage Vn and the output signal SOR when the dual mode charge pump 22 operates in its second mode. At time t1, the output signal SOR has relatively large amplitude, so the difference ΔV1 between the positive half-wave of the output signal SOR and the positive voltage Vp is relatively small, thereby having a better power efficiency. At time t2, the amplitude of the output signal SOR reduces, so the difference ΔV2 between the positive half-wave of the output signal SOR and the positive voltage Vp becomes larger, thereby having a poorer power efficiency. Moreover, the conventional audio amplifier requires external automatic test equipment (ATE) for testing whether the audio loop transition is correct, and thus requires higher test costs.
Charge pumps are well known circuits. For example, as disclosed by U.S. Pat. Publication No. 2011/0234305, FIG. 3 is a dual mode charge pump 22 which includes a flying capacitor Cf1 connected between bonding pads 56 and 58, a second flying capacitor Cf2 connected between bonding pads 60 and 62, an input terminal 64 receiving an input voltage Vin, output terminals 66 and 68 connected to output capacitors Co1 and Co2, respectively, a switch SW1 connected between the input terminal 64 and the bonding pad 56, a switch SW2 connected between the bonding pad 56 and the output terminal 66, a switch SW3 connected between the bonding pads 56 and 60, a switch SW4 connected between the bonding pad 58 and a ground terminal GND, a switch SW5 connected between the bonding pads 58 and 60, a switch SW6 connected between the bonding pads 58 and 62, a switch SW7 connected between the bonding pad 62 and the ground terminal GND, a switch SW8 connected between the bonding pad 62 and the output terminal 68, and a clock generator 54 providing signals CS1, CS2, CS3, CS4, CS5, CS6, CS7 and CS8 according to a gain information Gset for controlling the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and SW8, respectively. As shown in FIG. 3, the conventional dual mode charge pump 22 requires four bonding pads 56, 58, 60 and 62 for connection with two flying capacitors Cf1 and Cf2, causing higher packaging costs of an integrated circuit. Additionally, the dual mode charge pump 22 requiring two flying capacitors Cf1 and Cf2 needs eight switches SW1-SW8, making the costs and die area of the integrated circuit increased. Moreover, the conventional dual mode charge pump 22 can only provide the positive voltage Vp of either +Vin or +Vin/2 and the negative voltage Vn of either −Vin or −Vin/2, without capability of arbitrarily adjusting the positive voltage Vp or the negative voltage Vn.
FIG. 4 is a timing diagram of the signals CS1, CS2, CS3, CS4, CS5, CS6, CS7 and CS8 when the dual mode charge pump 22 of FIG. 3 provides the positive voltage Vp of +Vin2 and the negative voltage Vn of −Vin2. As can be seen in FIG. 4, the conventional dual mode charge pump 22 requires a three phase control to generate Vp=+Vin2 and Vn=−Vin2, causing its operation more complex.